(1) Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, it relates to a semiconductor memory device having a bit line chargeup circuit which charges a bit line within a minimum time period to ensure a fast readout operation.
(2) Description of the Related Art
In a semiconductor memory device such as a ROM device operating synchronously with clock signals, a bit line is charged up before reading out data therefrom. Depending on the memory content of the memory cell, the level of the bit line is either held at the precharging level or changed. By sensing the potential level of the bit line, the content of the memory is read out. This is made wide use of in semiconductor memory devices of the synchronous type.
Conventionally, precharging is usually performed by temporarily connecting a bit line to a power source. This connection is effected by applying a pulse of a fixed width to a switching transistor at predetermined timings to turn the transistor ON. However, with this method, it is difficult to set the width and timing of the pulse to the optimal values and some margin of error must be provided to ensure reliability of operation, resulting in some waste of access time. Specifically, in a memory device, there are many bit lines and the rising characteristics thereof differ. Therefore, the pulse width is determined as the time required for the precharging of the bit line with the slowest rising characteristics, plus a certain time (margin of error). The precharge timing is made the point of time before readout, wherein the precharging can be sufficiently effected (i.e., the pulse width can be secured). The pulse width, etc. includes elements of guesswork, therefore, to ensure reliability of operation, it must be made larger. In practice, therefore, a certain excess width is unavoidable.